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In the past , the VLSI ( Very Large Scale Integration ) designers were concerned and focused mainly on smaller silicon area , performance (higher calculation speed) , cost and reliability where as power considerations were given a secondary importance ; but due to huge increase in the demand , popularity and the number of users of the mobile devices (portable electronics) in the modern society , the primary concern of the VLSI designers has now been shifted to Power efficiency and Energy savings .  - . Normally , the circuits which display high performance and usually have a very complex structure as well as a dense integration , require a high clock frequency for faster operation , which in turn consumes power . . This , however , can be avoided if a new design is incorporated , one which would be consuming comparatively less power while maintaining comparable performance .
Power Consumption is affected by many factors ; leaving other design and frequency factors aside , however , it can be related as directly proportional to the square of the voltage supply . But voltage scaling would definitely affect the scaling of threshold voltage , which may cause the leakage power to rise exponentially . . Hence , this approach wouldn’t not provide much benefits . The complexity in a circuit design can be reduced by using synchronous clock inputs instead of an asynchronous one . Also , Edge Triggered Flip Flops are popularly used in modern VLSI designs and contribute majorly in the net power consumption by the circuit .
Now , there are mainly three components of power dissipation in a Flip Flop :- (1) Power consumed by internal and input nodes during the latching operations including the power dissipated driving the output load . (2) Power dissipated in the clock buffer that is driving the clock input of the Flip Flop . (3) Power dissipated in the logic gate that is driving the data input of the Flip Flop . Therefore , reducing the power dissipated due to clock and logic gates would definitely reduce the net power dissipated in a circuit .
The proposed Double Edge Triggered Flip Flop will double the frequency of data transfer for the same input clock cycle (or halve the input clock signal’s frequency for the same data transfer rate) , while working on comparatively similar voltages and dissipating comparatively similar power , hereby regulating the power dissipated in a circuit .
II. Double Edge Triggered Flip Flops (Basic Designs)
An Edge Triggered D-Flip Flop has a clock input (C) and a data input (D) . (Assumed that a positive Edge Triggered D-Flip Flop is used) . When C changes from 0 to 1 , the output (Q) assumes the value of D and holds it until the transition of C from 0 to 1 . Similarly , a negative Edge Triggered D-Flip Flop responds to the input data when C changes from 1 to 0 . Now , the most simplest version of a Double Edge Triggered D-Flip Flop would be two use two D-Flip Flop in such a way that one D-Flip Flop is sensitive to the rising edge of the clock while the second D-Flip Flop is sensitive to the falling edge , and to MUX (use a Multiplexer for deciding) the outputs of both the D-Flip Flops using the clock itself as a select .  . This easy , direct and intuitive approach is shown below :-
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In the above circuit , when C changes from 0 to 1 , the output assumes the input value of the D-Flip Flop present on the top (due to presence of the Multiplexer) , where as , when C changes from 1 to 0 , the output assumes the input value of the D-Flip Flop present at the bottom . In this way , the proposed Double Edge Triggered D-Flip Flop is able to respond to the input data twice per clock cycle , i.e. , this circuit would be able to transfer data at double the rate of transfer in the conventional D-Flip Flop while consuming comparatively similar power .
- Quote paper
- Rohit Daroch (Author), 2013, Double Edge Triggered Flip Flop, Munich, GRIN Verlag, https://www.grin.com/document/265932