The purpose of this thesis is to compare several filter topologies used for the decimation of sigma-delta modulated digital signals. The goal is to present optimized filter architectures with regard to an efficient VLSI implementation. A fifth-order 1-bit sigma-delta modulator using local feedback techniques will be considered as the front-end A/D converter. The subsequent digital filter reduces the sampling rate by a factor of 32. The decimation filter must guarantee a narrow transition band between 0.5 and 0.55 and stopband attenuation of 100dB.
Chapter 1 provides a brief introduction into the principles of digital signal processing. The considerations are focused on FIR filters due to the requirements for acoustic applications.
Chapter 2 illustrates the proposed overall structure and the design flow.
The objective of chapter 3 is to present the principles of oversampling data converters using sigma-delta techniques. The 5V fifth-order SigmaDelta-modulator with 90dB dynamic range (SNR+THD) will be presented, which has been fabricated in 1.2$um CMOS technology. For the sake of simplicity and robustness, a 1-bit quantizer will be used.
Chapter 4 deals with typical hardware realizations of digital filters. Apart from the ``brute force'' implementation of the multirate filter with identical filters running in parallel, also the LUT-based approach for small filter orders will be presented. Due to the advantages of compact implementation, the bit-serial approach and the bit-serial multiplier are investigated in detail.
In chapter 5 the straightforward one-stage multirate FIR filter will be introduced. To satisfy the specifications, a 4096 tap lowpass FIR filter will be designed. The influence of coefficient quantization is investigated and furthermore the ``block scaling'' method, to represent small values, is presented. The single-stage implementation becomes the more unattractive the higher the filter specifications are.
Chapter 6, therefore, focuses the investigations on cascaded structures. The first stage is realized as a comb or $sinc^K$ filter and decimates by a factor of 8 or 4. The frequently used conventional comb filter will be used but also a new architecture will be described. The new structure is based on the conventional comb filter with filter sharpening techniques to improve the frequency behavior. The unavoidable passband droop must be compensated for by the following lowpass FIR filter.
Inhaltsverzeichnis (Table of Contents)
- Introduction
- Overall Structure and Design Flow
- Oversampling Data Converters
- Hardware Realizations of Digital Filters
- Single-Stage Multirate FIR Filter
- Cascaded Structures
Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)
This thesis aims to compare various filter topologies used in the decimation of sigma-delta modulated digital signals, with a focus on efficient VLSI implementation. The goal is to present optimized filter architectures for a fifth-order 1-bit sigma-delta modulator with local feedback techniques used as the front-end A/D converter.
- Decimation of sigma-delta modulated digital signals
- Optimization of filter architectures for efficient VLSI implementation
- Comparison of different filter topologies
- Hardware realization of digital filters
- Influence of coefficient quantization on filter performance
Zusammenfassung der Kapitel (Chapter Summaries)
- Chapter 1: Provides a brief introduction to the principles of digital signal processing, focusing on FIR filters for acoustic applications.
- Chapter 2: Illustrates the proposed overall structure and the design flow of the decimation filter.
- Chapter 3: Presents the principles of oversampling data converters using sigma-delta techniques. The 5V fifth-order ΣA-modulator with 90dB dynamic range (SNR+THD) is presented, fabricated in 1.2μm CMOS technology.
- Chapter 4: Deals with typical hardware realizations of digital filters, including the "brute force" implementation of the multirate filter with identical filters running in parallel, as well as the LUT-based approach for small filter orders. The bit-serial approach and the bit-serial multiplier are investigated in detail due to their advantages for compact implementation.
- Chapter 5: Introduces the straightforward one-stage multirate FIR filter. A 4096 tap lowpass FIR filter is designed to meet the specifications. The influence of coefficient quantization is investigated, and the "block scaling" method for representing small values is presented. The single-stage implementation becomes less attractive as filter specifications increase.
- Chapter 6: Focuses on cascaded structures. The first stage is realized as a comb or sinc filter, decimating by a factor of 8 or 4. The conventional comb filter and a new architecture based on filter sharpening techniques are described. The unavoidable passband droop is compensated for by a subsequent lowpass FIR filter. Three examples, including comb-FIR cascade, sharpened comb-FIR cascade, and sharpened comb-half band filter cascade, are considered to compare filter realizations. The FIR filter realization using periodically time-varying coefficients (FIR-PTV filter) is also examined.
Schlüsselwörter (Keywords)
This study focuses on decimation lowpass filters for sigma-delta modulators, VLSI implementation, filter topologies, FIR filters, multirate architectures, coefficient quantization, comb filters, sinc filters, and FIR-PTV filters.
- Arbeit zitieren
- Dr. Rüdiger Kusch (Autor:in), 1998, Decimation Lowpass Filters for SIGMA-DELTA Modulators - A Comparative Study, München, GRIN Verlag, https://www.grin.com/document/19720
