Reference-Ladder Free Flash Analog to Digital Converter Architecture

Textbook , 2021 , 85 Pages , Grade: 10

Computer Science - Programming

In this book, the primary research objective is to design a novel comparator to get rid-off reference-ladder circuit. The design of power efficient Flash ADC is investigated by utilizing a novel power optimized single-ended comparator. The proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage
generation method for producing the reference voltage for the Flash ADC design. By employing optimized comparator, the Flash ADC achieves various benefits, as it does not require the necessity of a reference resistor ladder as well as front-end track and hold circuit. This reduces both layout area and power consumption and makes it appropriate
for System-on-Chip (SoC) ADC implementation
.
The basic structure of the single-ended comparator is modified CMOS Inverter. The performance of modified CMOS Inverter circuit is compared with the static CMOS Inverter. To demonstrate the functionality of the new comparator, 4-bit and 6-bit Flash ADCs has been designed and simulated under the environment of Cadence and LTspice CAD tools. For both of the Flash ADCs, a comparative analysis is presented with previously published works on Flash ADCs.

The secondary research objective is to propose a novel power reduction technique for high-speed Flash analog-to-digital converter, which not only reduces the power consumption in comparator but also examines the inactive comparators in the Flash ADC, thus inactive comparators get shutdown to save the unnecessary power consumption.This approach is based on two-step method of data conversion. By this method the total numbers of active comparators are reduced in comparison with the conventional Flash ADC. This feature of active comparators reduces the overall power consumption of the converter and the resultant architecture develops into power efficient Flash ADC architecture.

CONTENTS

Abbreviations

List of Figures

List of Tables

Chapter 1 Introduction
1.1 Overview
1.2 Motivation and Research Objective
1.3 book Organization

Chapter 2 Fundamentals of comparators & Analog-to-DigitalConverters
2.1 Introduction
2.1.1 Sampling
2.1.2 Amplitude Quantization
2.2 ADC Architectures
2.2.1 High-Speed ADCs
2.2.1.1. Flash ADC
2.2.1.2. Two-Step Flash ADC
2.2.1.3. Pipeline ADC
2.2.1.4. Time-Interleaved ADC
2.2.2 High-Resolution ADCs
2.2.2.1. Successive-Approximation-Register ADC
2.2.2.2. Sigma-Delta ADC
2.3 ADC Specifications
2.3.1 Offset & Gain Error
2.3.2 Differential & Integral Non-linearity
2.3.3 SNR & SNDR
2.3.4 Spurious-Free-Dynamic-Range
2.3.5 Effective Number of Bits
2.3.6 Dynamic Range
2.4 Conclusion

Chapter 3 Literature Review
3.1 Introduction
3.2 CMOS Comparator
3.2.1 Static Latched Comparators
3.2.2 Dynamic Latched Comparator
3.3 Flash ADC Design Issues
3.3.1 Reference-Ladder Bowing
3.3.2 Capacitive Loading
3.3.3 Input Signal Feed-through to Reference-Ladder
3.3.4 Kickback Noise
3.3.5 Bubbles (Sparkles) Generation
3.3.6 Metastability
3.3.7 Jitter Error
3.4 Flash ADCs Research Background
3.5 Conclusion

Chapter 4 A Novel Comparator Design for Flash ADC
4.1 Introduction
4.2 Modified CMOS Inverter for Flash ADC
4.2.1 Small signal voltage gain
4.3 Experimental Investigation of Modified Inverter
4.4 DC Analysis
4.4.1 Voltage Transfer Characteristic (VTC)
4.4.2 Power Dissipation
4.4.3 Variable Switching Voltage
4.4.4 Propagation Delay and Dynamic Power Consumption
4.5 Proposed Comparator
4.5.1 Voltage Transfer Characteristic
4.5.2 Simulation of Proposed Comparator
4.6 Conclusion

Chapter 5 Design of Flash Analog to Digital Converters
5.1 Introduction
5.2 Reference-ladder Free Flash ADC Architecture
5.3 Comparators array
5.4 Encoder for Flash ADC design
5.4.1 ROM Encoder
5.4.2 Wallace-Tree Encoder
5.4.3 MUX-Based Encoder
5.4.4 Gray Encoding
5.5 A 1-GS/s, 0.25-mW, 4-bit Flash ADC in UMC 180nm technology
5.5.1 Variable Switching Voltages
5.5.2 Thermometer to Binary Code Conversion
5.5.3 Transient Simulation
5.5.4 Simulation Results Comparison
5.6 A 1-GS/s, 2.1mW, 6-bit Flash ADC in 65nm PTM technology
5.6.1 Thermometer Code
5.6.2 Transient Simulation
5.6.3 Simulation Results Comparison
5.7 Conclusion

Chapter 6 A Novel Power Efficient Design of Flash Architecture
6.1 Introduction
6.2 Proposed Power Efficient Design of 4-bit Flash ADC
6.2.1 Proposed Comparator
6.2.2 Working Principle of the Proposed Flash ADC
6.3 Simulation of the proposed 4-bit Flash ADC
6.3.1 Transient Response
6.3.2 Result Summary

Chapter 7 Conclusion and Future Scope
7.1 Concluding Remarks
7.2 Future Work

Bibliography

ABBREVIATIONS

ADC Analog to Digital Converter

CMOS Complementary metal oxide semiconductor

DAC Digital to Analog Converter

DNL Differential Non-Linearity

DSP Digital Signal Processing

ENOB Effective Number of Bits

ERBW Effective Resolution Bandwidth

FFT Fast Fourier Transform

FOM Figure of Merit

GS/s Giga-Samples/second

IC Integrated Circuit

INL Integral Non-Linearity

LSB Least Significant Bit

MSB Most Significant Bit

NMOS Negative-channel metal oxide semiconductor

OSR Oversampling Ratio

PDP Power Delay Product

PMOS Positive-channel metal oxide semiconductor

ROM Read Only Memory

S&H Sample-and-hold

SAR Successive Approximation Register

SFDR Spurious Free Dynamic Range

SNR Signal to Noise Ratio

SNDR Signal to Noise and Distortion Ratio

SOC System on Chip

T&H Track-and-hold

VLSI Very Large Scale Integration

VTC Voltage transfer characteristics

LIST OF FIGURES

Fig. 2.1: Basic block diagram of Analog-to-Digital Converter

Fig. 2.2: Sampling process of track-and-hold circuit

Fig. 2.3: Comparator characteristics

Fig. 2.4: Amplitude Quantization

Fig. 2.5: Block diagram of Flash ADC

Fig. 2.6: Two-step Flash ADC architecture

Fig. 2.7: Input signal processing in a pipelined ADC

Fig. 2.8: Block diagram of a pipeline ADC

Fig. 2.9: Time-Interleaved ADC architecture

Fig. 2.10: Basic circuit diagram of the SAR ADC

Fig. 2.11: Iteration in SAR ADC

Fig. 2.12: Simplified block diagram of oversampling ADC

Fig. 2.13: First-order Sigma-Delta ADC

Fig. 2.14: Input-output transfer characteristic of ADC

Fig. 2.15: Illustration of Offset Error

Fig. 2.16: Illustration of Gain Error

Fig. 2.17: Illustration of DNL

Fig. 2.18: Illustration of SFDR

Fig. 3.1: General architecture of comparator

Fig. 3.2: Static latched comparator

Fig. 3.3: Static class-AB latched comparator II

Fig. 3.4: Dynamic latched comparator

Fig. 3.5: Comparator array's capacitance with input & output waveforms

Fig. 3.6: Input Signal Feed-through to reference ladder

Fig. 3.7: Kickback noise generation

Fig. 3.8: Bubble (Sparkle) Error generation .

Fig. 3.9: Clock Jitter

Fig. 3.10: Jitter Error

Fig. 4.1: CMOS Inverter a) Schematic b) Small signal model

Fig. 4.2: Modified CMOS Inverter a) Schematic b) Small signal model Fig.

Fig. 4.3: VTC a) CMOS Inverter b) Modified Inverter

Fig. 4.4: Node voltages v1 and v2 of Modified Inverter

Fig. 4.5: Drain current a) CMOS Inverter, b) Modified Inverter

Fig. 4.6: Power consumption a) CMOS Inverter, b) Modified Inverter circuit

Fig. 4.7: Switching voltage a) CMOS Inverter, b) Modified Inverter

Fig. 4.8: a) Power consumption, b) Propagation delay

Fig. 4.9: Proposed Comparator

Fig. 4.10: VTC of Proposed Comparator

Fig. 5.1: Reference-ladder free Flash ADC Architecture

Fig. 5.2: Wallace-tree encoder for 4-bit Flash ADC

Fig. 5.3: Multiplexer-based Encoder for 3-bit Flash ADC

Fig. 5.4: Gray encoding logic diagram for 3-bit Flash ADC

Fig. 5.5: Comparators array's output

Fig. 5.6: One-hot code waveform

Fig. 5.7: Encoder logic diagram

Fig. 5.8: Transient Simulation of 4-Bit Flash ADC

Fig. 5.9: Thermometer code waveforms

Fig. 5.10: Transient simulation of the 6-bit Flash ADC

Fig. 6.1: Detailed architecture of proposed 4-bit Flash ADC

Fig. 6.2: Schematic of the proposed comparator

Fig. 6.3: Functioning of comparator bank I

Fig. 6.4: Functioning of comparator bank II

Fig. 6.5: Functioning of comparator bank III

Fig. 6.6: Functioning of comparator bank IV

Fig. 6.7: Illustration of Comparator Banks output

Fig. 6.8: Transient Response of 4-Bit Flash ADC

Fig. 6.9: Comparison of active comparators

LIST OF TABLES

Table 2.1: Summary of Analog to Digital Converters

Table 3.1: Performance of Flash ADCs

Table 4.1: Comparison of Delay and Power for various levels of switching voltages

Table 4.2: Comparative analysis of proposed comparator

Table 4.3: Comparison of proposed comparator with dynamic comparators

Table 5.1: Gray Encoding

Table 5.2: Input & Output combination of OR Gate Encoder

Table 5.3: Encoder's Truth Table for 4-bit Flash ADC

Table 5.4: Comparative analysis of 4-bit Flash ADC

Table 5.5: Comparative analysis of 6-bit Flash ADC

Table 6.1: Performance Summary of designed 4-bit Flash ADC

Table 6.2: Comparator Counts for different resolution Flash ADCs

CHAPTER 1

INTRODUCTION

1.1 overview

Analog-to-digital converters (ADC's) are the universal and critical components of digital communication and digital signal processing (DSP) systems. The advancement of very- large-scale-integration (VLSI) has led to more complex DSP systems. These systems deal with diversity of analog signals including speech, medical imaging, satellite and various micro-sensor or transducer signals. The key to the success of DSP systems has been the advancement in ADC's 1. The ADCs basically convert analog information into digital signals for signal analysis and processing. Theoretically, an ADC executes the transformation of analog (continuous-time, continuous-amplitude) signal to digital (discrete-time, discrete-amplitude) signal.

There are number of ways to classify the analog-to-digital converter structures. Their architectures differ with respect to resolution, speed and power consumption. The different structures of ADC are explained in the subsequent chapter of this dissertation. High-speed ADCs have become important components of the high-speed data acquisition, communication and instrumentation systems 2-4. Among the variety of high-speed ADC architectures, Flash converter is the simplest and fastest ADC architecture. Flash ADC is the best candidate of choice, where maximum speed and moderate resolution is required. A unique application is the disk drive system, where the maximum read-write speed is required 5. The requirement for high-speed ADCs continues to increase in different area of communication including OFDM communication systems 19. However, there are additional applications in the field of wireless communication, where a Flash ADC gives adequate accuracy over the wide bandwidth, for instance in ultra-wideband (UWB) systems 20. Since many wireless applications are portable and battery driven. Recently, the requirement of low power and high speed ADC has been increased tremendously.

For instance, micro-sensor based wireless networks and implanted biomedical devices have turned into emerging application 22. These applications present an important restriction to the power consumption of the converters. The Flash ADC can be the leading component in terms of power consumption for entire analog frontend of such application.

However an N-Bit Flash ADC makes use of the 2N-1 comparators for data conversion. These comparators consume large power as they work simultaneously in parallel fashion. Comparator constitutes the fundamental building block in data converters and front-end component in digital signal processing applications. The selection of comparator directly affects the design of high-speed data conversion circuits in terms of speed and power consumption. Particularly for portable electronic equipment, the power consumption has become a key design feature in many electronic telecommunication systems employing ADC.

The traditional Flash architecture is constructed by an array of latched comparators and the design occupies large layout area and consumes high amount of power. In addition, the latched comparators suffer from significant kickback noise 25. The inputs nodes of the latched comparators are capacitive coupled with output nodes and due to this parasitic capacitance coupling, kickback noise is internally generated in the comparator. Since the analog input signal and reference ladder's signal is directly connected to comparator, therefore comparator inputs have unbalanced impedances and the kickback noise results in error in the ADC output 27. As a result, the optimization of the latched comparator becomes essential in designing of the Flash ADC.

1.2 Motivation and Research Objective

It is observed in literature review, that all high-speed ADC architecture containing Flash converters utilize the external reference-ladder circuit for generating the reference voltages. However, the presence of reference-ladder network creates lot of troubles. For instance, the static power consumption of Flash ADC gets increased and also its reference voltages may be affected by the charge injection, clock feed-through, kickback-noise and other nonlinearities of the comparators 13. As a result, the Flash ADC suffers from a large number of problems due to presence of reference ladder network.

In this book, the primary research objective is to design a novel comparator to get rid-off reference-ladder circuit. The design of power efficient Flash ADC is investigated by utilizing a novel power optimized single-ended comparator. The proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage generation method for producing the reference voltage for the Flash ADC design. By employing optimized comparator, the Flash ADC achieves various benefits, as it does not require the necessity of a reference resistor ladder as well as front-end track and hold circuit. This reduces both layout area and power consumption and makes it appropriate for System-on-Chip (SoC) ADC implementation.

The basic structure of the single-ended comparator is modified CMOS Inverter. The performance of modified CMOS Inverter circuit is compared with the static CMOS Inverter. To demonstrate the functionality of the new comparator, 4-bit and 6-bit Flash ADCs has been designed and simulated under the environment of Cadence and LTspice CAD tools. For both of the Flash ADCs, a comparative analysis is presented with previously published works on Flash ADCs.

The secondary research objective is to propose a novel power reduction technique for high-speed Flash analog-to-digital converter, which not only reduces the power consumption in comparator but also examines the inactive comparators in the Flash ADC, thus inactive comparators get shutdown to save the unnecessary power consumption.This approach is based on two-step method of data conversion. By this method the total numbers of active comparators are reduced in comparison with the conventional Flash ADC. This feature of active comparators reduces the overall power consumption of the converter and the resultant architecture develops into power efficient Flash ADC architecture.

1.3 Book Organization

In this book, an attempt has been made to design and realization of a novel power efficient Flash ADC for low power VLSI design. Here, a novel comparator and power reduction technique have been investigated for Flash converters. The simulation results are compared with existing reported Flash ADC. It is observed that the proposed technique reduces the power consumption significantly. The total text of the book is presented in seven chapters followed by references. The organization of book is as follows:

Chapter 1: Introduction: In this chapter, the various applications of high-speed ADCs are explored and discussed along with the aims and objectives of the research. The research emphasis is given on the power optimization of high-speed Flash ADC. At last, the book organization is presented.

Chapter 2: Fundamentals of Analog-to-Digital Converter: This chapter begins with the background of analog signal to digital signal conversion. The different ADCs architectures are discussed with their performance tradeoffs. Finally, this chapter concludes with explanation of main performance parameters of the ADCs.

Chapter 3: Literature Review: In this chapter, CMOS comparator as a building block of ADC and their classification has been introduced. The design issues of Flash architectures are thoroughly explained and examined. This chapter ends with the review of previously published works on the Flash ADCs.

Chapter 4: Novel Comparator Design for Flash ADC: In this chapter, the structure of modified CMOS Inverter and its improvements over static CMOS Inverter is explained. A comprehensive analysis of Inverter and its modified circuit is carried out to suggest the circuit as comparator for Flash ADC design. Using the same circuit, the proposed comparator circuit is simulated and examined for designing the Flash ADC.

Chapter 5: Flash ADC design: This chapter covers the design details of the 4-bit & 6- bit Flash ADC using proposed comparator. The designed Flash ADCs does not require the reference-ladder network. The different encoder for Flash ADCs are classified and discussed.

Chapter 6: Power Efficient Flash ADC Architecture: In this chapter, a novel power reduction technique has been introduced for high-speed Flash ADC. The technique examines the inactive comparators in the Flash ADC and disables them to save the unnecessary power consumption. The 4-bit Flash ADC is designed for the demonstration purpose.

Chapter 7: Conclusion: This chapter is concluded with remarks covering the work of the book. At last, the future scope of the work has been revealed and discussed.

CHAPTER 2

FUNDAMENTALS OF ANALOG-TO-DIGITAL CONVERTERS

2.1 Introduction

Analog to digital converter basically acts as an interface between analog signal and digital signal. The basic block diagram of ADC is shown in Fig. 2.1. The analog signal is converted into digital signal in three steps. The very first step is sampling, that is the quantization of the analog signal in the time domain. Thereafter, amplitude quantization is processed by the comparator. However, the amplitude quantization introduces the error (quantization error) in the ADC. The performance of ADC is greatly affected by the quantization error. Sampling and amplitude quantization are two important operations in analog to digital conversion 14. At last, amplitude quantized signal is converted into the digital codes by the encoder.

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Fig. 2.1: Basic block diagaram of Analog-to-Digital Converter.

2.1.1 Sampling

The Sample-and-Hold (S&H) circuit constitutes an essential part in most of the ADC architecture 13. It is particularly essential in ADCs to ensure the analog input signal at a constant level during the conversion process. The S&H circuit performs the sampling operation. In this sampling scheme, the S&H circuit tracks the analog signal during sampling (sampling mode) and remains at the last steady value (hold mode) until the amplitude quantization is completed. The sampling process of S&H circuit is shown in the Fig. 2.2. In literature, the S&H circuit is also known as Track-and-Hold (T&H) circuit.

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Fig. 2.2: Sampling process of Sample-and-hold circuit

Here x(t) indicates the analog input signal and signal g(t) denotes the output of the S&H circuit, while the x(KT) represents the sampled signal at the Kth instant of time. The signal g(t) is discrete-time signal but still is continuous in amplitude. Therefore, the next process in ADC is the conversion of discrete-time signal into digital signal (discrete­time discrete-amplitude signal).

2.1.2 Amplitude Quantization

The fundamental operation of an analog-to-digital converter (ADC) is the amplitude quantization of the analog signal.

The basic analog signal and quantized signal are presented in the Fig 2.3.

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Fig. 2.3: Amplitude Quantization

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Fig. 2.4: Comparator's characteristic

The comparator does the operation of amplitude quantization, which is the comparison of analog signal with pre-defined reference signal. The elementary function of a comparator is to compare an analog signal with the reference signal. The output digital signal is basically a binary signal either VOL or VOH derived from comparison. The voltage transfer characteristic of a comparator is shown in Fig. 2.4. The ideal characteristic is shown in the Fig. 2.4 (a). If input voltage is greater than reference voltage i.e. Vin > Vref , then the comparators output is high i.e. VOH (logic “1”) otherwise its output is low i.e. VOL (logic “0”).

However, the actual characteristic of comparator is different from ideal transfer characteristic 14. It is shown in Fig. 2.4 (b), the output voltage is given by the following equation 2.2.

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Vos is the offset voltage of the comparator; it does not only affect the quantization process but also affects the overall accuracy of analog-to-digital converters.

Quantization process intrudes noise in the signal. It is inversely proportional to the resolution of ADC. The intensity of quantization noise becomes smaller with higher resolution of ADC. It is due to the fact that, the high resolution increase the number of reference levels for quantization. As a result, the signal is divided into a greater number of reference levels and the weight of LSB becomes smaller. This in turn decreases the maximum quantization error. In the ADC, the theoretical value signal-to-noise ratio (SNR) input is obtained from quantization noise as given by equation 2.3.

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2.2 ADC Architectures

In the literature of ADC, speed and resolution are the two important design parameters of ADCs. Accordingly, the ADC architectures can be broadly classified in two categories namely High-Speed ADC and High-Resolution ADC 14. Generally, there is trade-off between speed and resolution parameters of ADC. The High-speed ADCs are generally low resolution ADCs, while high-resolution ADCs suffer from low-speed of conversion. In this Section, these ADCs architectures are discussed with their performance tradeoffs.

2.2.1 High-Speed Analog-to-Digital Converters

The eminent architecture for high-speed ADC is the Flash architecture. In this architecture, a group of comparators compare the analog signal to well-defined evenly spaced reference signals. Subsequently, the functioning of Flash architecture is explained and elaborated in the subsequent Section. In addition to Flash architecture, the high-speed ADCs include Two-step Flash, Subranging and Pipeline architecture.

2.2.1.1 Flash ADC

The Flash ADC includes total 2n-1 number of comparators for the conversion. The amplitude quantization is performed by the comparison of the input signal to all 2N-1 reference levels in a single clock cycle 16. Due to parallel comparison, the Flash ADC architecture offers the highest conversion rate.

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The reference levels are usually obtained by a resistive ladder network of 2N equally sized resistor. In the comparison process, each one of the 2N-1 comparator will decide whether the input signal is greater or lesser than the reference level and generates ‘1' or ‘0' respectively. The comparators output forms the thermometer code. A ROM encoder or equivalent encoder is then utilized to translate the thermometer code into n-bit digital code. In the Flash architecture, all of the 2N-1 comparators work as the implicit sample and hold (S&H) circuit. Due to parallel architecture of comparators, the input is being tracked by all the comparators simultaneously. Therefore Flash ADC architecture does not require explicit sample and hold circuits. Hence Flash ADC architecture works faster than the other S&H employed ADCs architecture.

However, in spite of high speed and simple architecture, Flash ADC goes through number of disadvantages. One of the drawbacks of the Flash architecture is high input­capacitance resulting from the parallel architecture of the comparators.

For low resolutions application, the Flash architecture is most appropriate ADC. As resolution increases by 1 bit, the number of comparators gets almost doubled and the power consumption increases exponentially. Therefore, the hardware area and power dissipation typically confines a Flash ADC's for high resolution application. The exponential increase in capacitance, power and area normally limits Flash ADC resolution lesser than 8 bits 1.

2.2.1.2 Two-Step Flash ADC

Flash ADC is most favorable architecture for very high-speed but impractical for high resolution converters. In Flash architecture, the parameters (power dissipation, area and input capacitance) increase exponentially with the resolution of ADC. This exponential growth makes Flash ADC impractical for higher resolution. Consequently, trade-off has been formulated between the resolution and speed. The Two-Step Flash ADC is designed to relax the exponential relation of power with resolution of Flash ADC 16.

Fig. 2.6 shows the basic structure of a two-step Flash ADC. It employs a sample-and­hold at the input to drive an N1-bit course Flash ADC for coarse conversion of MSBs. The DAC converts the N1-bit back to an analog signal, which is subtracted from the input to generate the residue (course quantization error). Next, the residue is converted into digital signal by a second N2-bit Flash ADC, which yields the LSB (fine conversion).

The digital logic combines coarse and fine results to obtain the final N (N1+N2) output bits. In two-step Flash ADC, the conversion does not occur promptly as in the conventional Flash ADC. In this type of ADC, the analog to digital conversion takes place in two numbers of steps. This ADC is also known as sub-ranging Flash ADC 14.

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It is obvious that the number of comparators required for a two-step or a sub-ranging is much lesser than the number for a Flash ADC. The number of comparators required in a Flash ADC is 2N1+N2-1. While two-step Flash ADC requires only 2N1+2N2 -2 comparators. The clear disadvantage of two-step Flash ADC is the decreased conversion-rate as compared to full-Flash ADC.

2.2.1.3 Pipeline ADC

Pipeline ADC exploits the principle of sub-ranging algorithm of conversion. In actual practice, it makes use of more than two sub-ADCs. Each sub-ADC has a resolution of only two or three bit 18.

To get the better insight of pipeline ADC, a 4-bit pipeline ADC is taken as an example, which consists of 4 stages (S1 to S4) of 1-bit resolution sub-ADCs. The input range (0 to Vref) is divided into two reference level by Vref/2. The first stage sub-ADC compares the input with the middle level of Vref. Since the input is greater than the Vref/2, the first stage sub-ADC S1 produces a digital “1” and subtracts Vref /2 from the input signal.

Thereafter, stage S1 amplifies the residue by a factor of two. It is applied to the next stage. Stage S2 performs the same operation. S2 compares the input to Vref /2. Because S2's input is smaller than Vref /2, S2 outputs a digital “0” and subtracts nothing from S2's input .S2 amplifies its residue and applies the result to S3. S3 and S4 follow the same steps, with their digital outputs being “1” and “1”.

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Fig. 2.7: Input signal processing in a pipeline ADC

The pipeline architecture with J stages is shown in Fig. 2.8. Each stage generates an analog output, which is fed to the next stage of the pipeline. The first pipeline stage determines N1 bits; the second pipeline stage generates N2 bits and K stage produces NK bits. Then the overall resolution of pipeline ADC N=N1 + N2 + ••• + Nk bits.

The overall resolution of the pipeline ADC is the sum of each pipeline stage's resolution. The disadvantage of pipeline ADC is the increased latency time with the number of pipeline stages. In general, a pipelined ADC is derived from a pipelining of several low resolution Flash ADCs 16.

The generic structure of single pipeline stage is also shown in Fig. 2.8.

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Fig. 2.8: Block diagram of a pipeline ADC

The sub-ADC produces k-bit while the DAC converts the sub-ADC output back into analog signal. The DAC output and VIN are subtracted to produce quantization error of ViN, thereafter amplified quantization error determines the new residue voltage Vres(j) for the next pipeline stage. This process of residue voltage generation is described mathematically 14 as;

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2.2.1.4 Time-Interleaved ADC

The Time-Interleaved ADC (TI-ADC) is not a fundamental type of ADC architecture. As in the Flash ADC, large numbers of comparators are associated in parallel configuration; Similar to Flash architecture the Time-Interleaved ADC makes use of parallelism of several ADCs (sub-ADCs). The sample times of the sub-ADCs are timely interleaved.

The block diagram of TI-ADC is shown in the Fig. 2.9. If M sub-ADCs are interleaved in the TI-ADC, then sample time of each sub-ADC will come on every Mth clock cycle. And the sampling frequency will be divided by M. The sub-ADCs may be any fundamental ADC like Flash, pipeline, SAR ADC.

The analog signal is applied to a Sample-and-hold (S&H) circuit, and then an analog DEMUX allocates the sampled signal to the one of the sub-ADCs. The sub-ADCs are clocked sequentially by the clock generated by the clock divider. All the sub-ADCs are interleaved in time. When a sub-ADC has completed its conversion, its digital outputs are fed through the digital multiplexer.

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Fig. 2.9: Time-interleaved ADC architecture

As the architecture of the sub-ADCs can be different significantly, Offset and gain mismatches among sub-ADCs may cause spurious harmonics in the output spectrum. A calibration technique is essential to reduce offset and gain mismatches to attain best possible performance. The TI-ADC offers the considerable benefit of selecting the sub­ADC architecture. SAR ADCs, Flash ADCs and pipeline ADCs compose these architectures very attractive for time-interleaving.

2.2.2 High-Resolution Analog-to-Digital Converters

The High-Resolution ADCs are another category of data converters. These ADCs consumes less power in comparison with high-speed ADCs. The successive- approximation-register (SAR) and sigma-delta ADCs are two important categories of high-resolution ADCs.

2.2.2.1 Successive-Approximation-Register ADC

Fig. 2.10 shows a simplified block diagram of successive-approximation register (SAR) ADC. The SAR ADC makes use of only single high-speed and high-precision comparator recursively 13. The SAR architecture comprises three main components namely comparator, register and digital to analog convertor (DAC).

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Fig. 2.10: Basic circuit diagram of the SAR ADC.

The basic principle of SAR is based on binary search algorithm 13. Initially, the content of successive-approximation-register is set to midscale (10000) by setting MSB of the register content to digital logic “1”. As a result the DAC produces midscale analog voltage Vfs/2. The DAC output demonstrates the conversion process of SAR ADC as shown in the Fig. 2.11. If, the input signal is higher than the DAC output i.e. Vs > Vdac. The comparator directs the SAR to maintain the MSB at digital logic “1”.

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Fig. 2.11: Iteration in SAR ADC

If Vs < Vdac, the MSB of SAR is set to “0”. After that, the next bit of SAR is set to “1”. Subsequently the DAC output set to new value higher or lesser than Vfs/2. Once again, the comparator compares Vs and Vdac and directs SAR accordingly.

For N bit resolution, this process lasts for N cycles. Therefore the speed of the SAR ADC is much slower but at the same time it consumes lesser power as compared to other types of ADC. In general, the speed of SAR ADCs is restricted to tens of megahertz while the resolution attains as high as 16 bits.

2.2.2.2 Sigma-Delta ADC

Sigma-Delta ADC is the special type of high-resolution ADC. This type of ADC samples the analog signal at a very high rate. The sampling rate is much higher than the bandwidth of the signal. Because of this reason, Sigma-Delta ADC is also known as oversampling ADC.

Generally, SAR ADC is employed in the application, in which high resolution is required. However, in SAR ADC, high speed sample and hold (S&H) circuit and comparator are required. This high-precise factor presents the restrictions on realization of a very high resolution ADC. In Sigma-Delta ADC, the precise and high speed S&H circuit is not required and less hardware is needed as shown in the Fig. 2.12.

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Fig. 2.12: Simplified Block diagram of oversampling ADC

As a result, the Sigma-Delta ADC makes an alternate choice for high resolution ADC 13. The amplitude quantization is carried out with the modulator and encoding of quantized signal is performed with the digital filter. A sigma-delta modulator consists of an integrator, 1-bit ADC and 1 bit- DAC. The working principle of sigma-delta ADC is shown in Fig. 2.13.

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Fig. 2.13: First-order Sigma-Delta ADC

The quantization error is the difference between the analog signal and feedback signal (DAC output). The quantization error is integrated by the integrator. In order to convert an analog signal to digital signal, the sigma-delta ADC employs the negative feedback to converge the error to zero. As a result of oversampling, a sigma-delta ADC can attain a high resolution as high as 20 bits.

2.3 ADC's Specification

For proper design of ADC, it is very important to be familiar with performance parameters of analog-to-digital converter. The performance parameter (ADC's specification) can be classified into two categories namely Static (DC) specification and Dynamic specification. The DC specification actually specifies the accuracy of a converter.

The input-output (I/O) transfer characteristic of ADC is the foundation of all the Static specifications; however, the I/O transfer characteristic illustrates the static performance of an ADC. The ideal I/O characteristic of ADC is a staircase waveform with identical steps over the entire dynamic range. However the actual I/O transfer characteristic is different than ideal transfer characteristic 31.

The difference between actual and ideal I/O transfer characteristic is shown in Fig. 2.14. An ideal N-bit ADC converts a continuous, analog input signal into a time discrete, quantized digital word. If the inputs signal amplitude scale is from zero to full-scale voltage (VFS) the ideal step corresponding to the least significant bit of a converter is VLSB as given by equation 2.5.

Abbildung in dieser Leseprobe nicht enthalten

Fig. 2.14: Input-output transfer characteristic of ADC.

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• College: Manipal University Jaipur
• Grade: 10
• Author: Gulrej Ahmed (Author)
• Publication Year: 2021
• Pages: 85
• Catalog Number: V1160930
• ISBN (PDF): 9783346564108
• ISBN (Book): 9783346564115
• Language: English
• Tags: reference-ladder, free, flash, analog, digital, converter, architecture