In this book, the primary research objective is to design a novel comparator to get rid-off reference-ladder circuit. The design of power efficient Flash ADC is investigated by utilizing a novel power optimized single-ended comparator. The proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage
generation method for producing the reference voltage for the Flash ADC design. By employing optimized comparator, the Flash ADC achieves various benefits, as it does not require the necessity of a reference resistor ladder as well as front-end track and hold circuit. This reduces both layout area and power consumption and makes it appropriate
for System-on-Chip (SoC) ADC implementation
.
The basic structure of the single-ended comparator is modified CMOS Inverter. The performance of modified CMOS Inverter circuit is compared with the static CMOS Inverter. To demonstrate the functionality of the new comparator, 4-bit and 6-bit Flash ADCs has been designed and simulated under the environment of Cadence and LTspice CAD tools. For both of the Flash ADCs, a comparative analysis is presented with previously published works on Flash ADCs.
The secondary research objective is to propose a novel power reduction technique for high-speed Flash analog-to-digital converter, which not only reduces the power consumption in comparator but also examines the inactive comparators in the Flash ADC, thus inactive comparators get shutdown to save the unnecessary power consumption.This approach is based on two-step method of data conversion. By this method the total numbers of active comparators are reduced in comparison with the conventional Flash ADC. This feature of active comparators reduces the overall power consumption of the converter and the resultant architecture develops into power efficient Flash ADC architecture.
Table of Contents
Chapter 1 Introduction
1.1 Overview
1.2 Motivation and Research Objective
1.3 book Organization
Chapter 2 Fundamentals of comparators & Analog-to-Digital Converters
2.1 Introduction
2.1.1 Sampling
2.1.2 Amplitude Quantization
2.2 ADC Architectures
2.2.1 High-Speed ADCs
2.2.1.1. Flash ADC
2.2.1.2. Two-Step Flash ADC
2.2.1.3. Pipeline ADC
2.2.1.4. Time-Interleaved ADC
2.2.2 High-Resolution ADCs
2.2.2.1. Successive-Approximation-Register ADC
2.2.2.2. Sigma-Delta ADC
2.3 ADC Specifications
2.3.1 Offset & Gain Error
2.3.2 Differential & Integral Non-linearity
2.3.3 SNR & SNDR
2.3.4 Spurious-Free-Dynamic-Range
2.3.5 Effective Number of Bits
2.3.6 Dynamic Range
2.4 Conclusion
Chapter 3 Literature Review
3.1 Introduction
3.2 CMOS Comparator
3.2.1 Static Latched Comparators
3.2.2 Dynamic Latched Comparator
3.3 Flash ADC Design Issues
3.3.1 Reference-Ladder Bowing
3.3.2 Capacitive Loading
3.3.3 Input Signal Feed-through to Reference-Ladder
3.3.4 Kickback Noise
3.3.5 Bubbles (Sparkles) Generation
3.3.6 Metastability
3.3.7 Jitter Error
3.4 Flash ADCs Research Background
3.5 Conclusion
Chapter 4 A Novel Comparator Design for Flash ADC
4.1 Introduction
4.2 Modified CMOS Inverter for Flash ADC
4.2.1 Small signal voltage gain
4.3 Experimental Investigation of Modified Inverter
4.4 DC Analysis
4.4.1 Voltage Transfer Characteristic (VTC)
4.4.2 Power Dissipation
4.4.3 Variable Switching Voltage
4.4.4 Propagation Delay and Dynamic Power Consumption
4.5 Proposed Comparator
4.5.1 Voltage Transfer Characteristic
4.5.2 Simulation of Proposed Comparator
4.6 Conclusion
Chapter 5 Design of Flash Analog to Digital Converters
5.1 Introduction
5.2 Reference-ladder Free Flash ADC Architecture
5.3 Comparators array
5.4 Encoder for Flash ADC design
5.4.1 ROM Encoder
5.4.2 Wallace-Tree Encoder
5.4.3 MUX-Based Encoder
5.4.4 Gray Encoding
5.5 A 1-GS/s, 0.25-mW, 4-bit Flash ADC in UMC 180nm technology
5.5.1 Variable Switching Voltages
5.5.2 Thermometer to Binary Code Conversion
5.5.3 Transient Simulation
5.5.4 Simulation Results Comparison
5.6 A 1-GS/s, 2.1mW, 6-bit Flash ADC in 65nm PTM technology
5.6.1 Thermometer Code
5.6.2 Transient Simulation
5.6.3 Simulation Results Comparison
5.7 Conclusion
Chapter 6 A Novel Power Efficient Design of Flash Architecture
6.1 Introduction
6.2 Proposed Power Efficient Design of 4-bit Flash ADC
6.2.1 Proposed Comparator
6.2.2 Working Principle of the Proposed Flash ADC
6.3 Simulation of the proposed 4-bit Flash ADC
6.3.1 Transient Response
6.3.2 Result Summary
Chapter 7 Conclusion and Future Scope
7.1 Concluding Remarks
7.2 Future Work
Research Objectives and Themes
The primary objective of this work is to design a novel power-efficient comparator for Flash Analog-to-Digital Converters (ADCs) that eliminates the need for an external reference-ladder circuit. Additionally, the research proposes a power reduction technique for high-speed Flash ADCs by disabling inactive comparators during operation.
- Design of a novel, power-optimized single-ended comparator utilizing modified CMOS inverter structures.
- Elimination of the traditional resistive reference-ladder network and front-end track-and-hold circuits.
- Development of a power reduction technique using a two-step data conversion method to minimize active comparator counts.
- Implementation and comparative performance analysis of 4-bit and 6-bit Flash ADCs using various technology nodes (180nm, 65nm).
Excerpt from the Book
3.3.4 Kickback Noise
Generally, Flash ADC makes use of regenerative types of comparator. During regeneration phase, the comparators itself generates the noise at their input terminals. As a consequence, input signal and the reference ladder voltage get corrupted. This kind of noise is known as kickback noise and it varies as a relation of square of the number of comparators. The following Fig. 3.7 demonstrates the generation of kickback noise [27].
Suppose the comparator works in regeneration phase, noise is induced on the input terminals by the voltage excursion (0 to VDD) of output terminals. This is due to coupling of input terminal to output terminal through the parasitic capacitances of the devices. The kickback affects not only the input signal, but also the reference-voltage of the reference ladder network.
Summary of Chapters
Chapter 1 Introduction: This chapter introduces the role of ADCs in DSP systems and outlines the research objective of designing a power-efficient, reference-ladder free Flash ADC.
Chapter 2 Fundamentals of comparators & Analog-to-Digital Converters: This chapter provides background on analog-to-digital conversion processes, different ADC architectures, and critical performance parameters.
Chapter 3 Literature Review: This chapter reviews comparator design methodologies and examines common design challenges in Flash ADCs, such as kickback noise and reference-ladder bowing.
Chapter 4 A Novel Comparator Design for Flash ADC: This chapter explains the design and analysis of a modified CMOS inverter-based comparator aimed at reducing power and propagation delay.
Chapter 5 Design of Flash Analog to Digital Converters: This chapter details the design of reference-ladder free 4-bit and 6-bit Flash ADCs and evaluates their performance against previously published works.
Chapter 6 A Novel Power Efficient Design of Flash Architecture: This chapter introduces a technique to reduce power consumption by managing active and inactive comparator banks in a two-step architecture.
Chapter 7 Conclusion and Future Scope: This chapter summarizes the research achievements regarding power optimization in Flash ADCs and suggests future directions for implementation in deep submicron technologies.
Keywords
Flash ADC, CMOS Inverter, Comparator Design, Low Power, Reference-Ladder Free, Power Efficiency, Kickback Noise, VLSI, Analog-to-Digital Conversion, Signal Processing, Metastability, Propagation Delay, Dynamic Power, Threshold Voltage, Data Converters
Frequently Asked Questions
What is the primary focus of this research?
The research focuses on the architectural design of high-speed, power-efficient Flash Analog-to-Digital Converters (ADCs), specifically aiming to remove the traditional reference-ladder network.
What are the central theme fields of this book?
The central themes include low-power VLSI design, CMOS comparator optimization, Flash ADC architectures, and techniques for minimizing power dissipation in data conversion systems.
What is the main research objective?
The primary objective is to design a novel, power-optimized single-ended comparator that generates its own threshold voltage, thereby eliminating the need for bulky external resistor ladders and track-and-hold circuits.
Which scientific methods are utilized?
The research utilizes theoretical circuit modeling, mathematical derivation of performance metrics (like gain and switching voltage), and extensive simulation using industry-standard tools like Cadence Virtuoso and LTspice.
What topics are covered in the main body?
The main body covers the fundamentals of ADC operation, a literature review of existing comparator topologies, the design and DC analysis of a modified CMOS inverter, and the implementation of 4-bit and 6-bit Flash ADC designs.
How is the power efficiency achieved?
Power efficiency is achieved by using a modified CMOS inverter structure as a comparator and implementing a sub-ranging power reduction technique that shuts down inactive comparators in the Flash ADC array.
How does the proposed comparator differ from a traditional TIQ comparator?
The proposed comparator utilizes an optimized modified inverter structure with header and footer transistors that provide a high resistive path, significantly reducing drain current and power consumption compared to the conventional Threshold Inverter Quantization (TIQ) approach.
Why is the reference-ladder network problematic in Flash ADCs?
The reference-ladder network contributes to high static power consumption and is susceptible to non-idealities like charge injection, clock feed-through, and kickback noise, which can degrade the overall accuracy of the converter.
- Quote paper
- Gulrej Ahmed (Author), 2021, Reference-Ladder Free Flash Analog to Digital Converter Architecture, Munich, GRIN Verlag, https://www.grin.com/document/1160930
