A Study and Comparison of Low Voltage CMOS Current Multiplier

Studienarbeit, 2011
5 Seiten


Abstract- A study and comparison between current mode CMOS analog multiplier, CMOS current mode multiplier/divider and high frequency four quadrant current multiplier has been carried out in this paper. Current multiplier has been simulated in SPICE with 0.35μm, 0.5µm. Simulation have been done with supply voltage of 3.3V, 1.5V and 1.55V respectively. The simulated results show that characteristic of multipliers are linear with 10μA, 10μA and 30μA input range respectively. These circuits are widely used for analog signal processing application.


Multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is not only used as a computational building block but also as a programming element in system such as filters, mixers, synthesizers, converter and modulators in communication systems. These are also important for non-linear analog signal processing functions finding application in adaptive filtering, modulation, fuzzy integrated system, frequency translation, automatic gain controlling and neural network [6]. Current multiplier can be designed either using transistor in linear region, in saturation region.

Main feature of standard CMOS fabrications are simplicity, low voltage operation, low power consumption and wide dynamic current range. In addition it is insensitive to temperature and process variation [7].


A. Low voltage current mode CMOS analog multiplier:

The principle of operation of the multiplier is based on the square-difference identity. There are three steps as shown in fig.1. and described as below:

1. Sum and subtraction both inputs.

2. Take the square of terms of first step and divided it by a constant current i.e. 4I.

3. Subtraction of second step with each other that output can be expressed as [5].

illustration not visible in this excerpt

Figure 1. Current –Mode analog multiplier circuit

Current-mode squarer circuit based on the dual translinear loop. The circuit consists of two dual translinear loops. The first loop transistor Mp1 to Mp4 provides a (X-Y) input function to the squarer circuit provides output (X-Y) 2. The second loop transistor Mp6 to Mp9 provides a (X+Y) input function to the squarer circuit provides output (X+Y) 2 [6].

Solving these equations we get:

Thus output current is directly proportional to Ix and Iy and inversely proportional to Ib . In this Ib is constant equal to 10µA [6].

Figure 2. Current mode analog multiplier

B. Low voltage CMOS current-mode multiplier/divider:

The approach followed to implement the current mode multiplier will be the combination of geometric mean circuit and a squarer/divider circuit. Consider the following expression [7]:


Where Ix, Iy, Iw and Iz being the current signals.

As shown in fig.3 output of squarer/divider circuit is


Iz is output current so we can write as:


Hence output current is:


illustration not visible in this excerpt

Figure 3. Current-mode multiplier/divider

Fig.4. shows the circuit implementation of current-mode multiplier/divider. It is based on forcing transition from triode region to saturation region and vice versa in transistor MN4, MN6, MN10 and MN12.Transistor MN2, MN8, MN10 and MN16 always operates in saturation, which can be done by properly choosing the cascade bias voltage Vcn. It will be assumed that the threshold voltage Vth of all NMOS transistor is same and that transistor MN2, MN8, MN10, MN16, MN4, MN6, MN12 and MN14 are matched, having the same transconductance factor Transistor MN1, MN3, MN5, MN7, MN9, MN11, MN13 and MN15 are also matched. Aspect ratio of MN1, MN3, MN5, MN7, MN9, MN11, MN13 and MN15 is n2 times larger than the aspect ratio of transistor MN2, MN4, MN6, MN8, MN10, MN12, MN14 and MN16, n being an integer greater than one [7].

illustration not visible in this excerpt

Figure 4. Current-mode multiplier/divider

C. High frequency four quadrant current multiplier:

Four quadrant CMOS current multiplier categorized into two groups: i.e. switched-capacitor approach and continuous time approach [4]. The multiplier based on switched capacitor approach has many disadvantages such as band limited signals and aliasing. So we will implement the circuit using continuous time approach. In this approach transistor could be biased in weak or strong inversion region. Generally transistor operates in saturation region because the square-algebraic identity can be easily realized [4].

Fig. 5. shows the four quadrant current multiplier. By using quadratic relation between the input and output currents we can find [4]:


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A Study and Comparison of Low Voltage CMOS Current Multiplier
Guru Jambheshwar University of Science & Technology
ISBN (eBook)
624 KB
study, comparison, voltage, cmos, current, multiplier
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Mohit Kumar (Autor)Sandeep Arya (Autor)Manoj Kumar (Autor), 2011, A Study and Comparison of Low Voltage CMOS Current Multiplier, München, GRIN Verlag, https://www.grin.com/document/174784


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