Adders are one of the widely used digital components in digital integrated circuit design. Addition is the basic operation used in almost all computational systems. Therefore, the efficient implementation and design of arithmetic units requires the binary adder structures to be implemented in an equally efficient manner. A ripple carry adder has smaller area but less speed. A carry look-ahead adder is faster though its area requirements are high. Carry select adders (CSLA) lie in middle. In this work a novel carry select adder using Binary Excess Converter (BEC) is proposed. It provides good compromise between cost and performance thereby establishing a proper trade-off between time and area complexities. In this work Tanner EDA is used for the comparison of all adders – Ripple carry adder, Bitwise carry select adder, Square root carry select adder, proposed carry select adder using BEC.
Inhaltsverzeichnis (Table of Contents)
- I. Introduction
- II. Regular Carry Select Adder
- III. Binary Excess Convertor (BEC)
- IV. Proposed Carry Select Adder
- V. Results
- VI. Conclusion
- VII. References
Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)
This work aims to design and develop a high-performance, low-area, and low-power carry select adder using a Binary Excess Converter (BEC). The paper investigates the benefits of using BEC in place of a traditional Ripple Carry Adder (RCA) within the Carry Select Adder (CSLA) architecture. The primary objectives are to reduce area and power consumption while maintaining speed. Key themes include:- High-speed adder design for digital circuits
- Optimization of area and power consumption in adders
- Implementation of Binary Excess Converter (BEC) in CSLA architecture
- Comparison of different adder implementations
- Performance evaluation through simulations and analysis
Zusammenfassung der Kapitel (Chapter Summaries)
- I. Introduction: This chapter introduces the importance of high-speed adders in modern digital circuits. The need for area and power efficiency is highlighted, with a focus on the trade-offs between different adder architectures like ripple carry adders and carry look-ahead adders. The carry select adder (CSLA) is presented as a promising option for achieving a balance between speed and resource usage.
- II. Regular Carry Select Adder: This chapter details the functioning and advantages of the regular carry select adder (CSLA). The chapter describes how CSLA overcomes carry propagation delays in traditional adders by utilizing multiple ripple carry adders (RCA) in parallel. The benefits of CSLA, such as reduced propagation delay, are emphasized.
- III. Binary Excess Convertor (BEC): This chapter introduces the Binary Excess Converter (BEC) as a key component of the proposed adder design. It provides a detailed explanation of the BEC's structure and its advantages over traditional full adders, including reduced gate count. The chapter includes illustrative diagrams and waveform explanations for a 4-bit BEC.
- IV. Proposed Carry Select Adder: This chapter presents the novel carry select adder (CSLA) architecture incorporating the BEC. It explains the modification of the square root CSLA (SQRT CSLA) architecture by replacing the RCA with BEC. The chapter discusses how this replacement leads to significant reductions in area and power consumption. Detailed schematics and figures illustrate the proposed architecture and its implementation.
- V. Results: This chapter presents simulation results and a comparison of the proposed CSLA with the regular SQRT CSLA in terms of area, power consumption, and delay. The results demonstrate significant improvements in area and power efficiency achieved through the BEC modification.
Schlüsselwörter (Keywords)
This work focuses on designing and analyzing a high-performance carry select adder using a Binary Excess Converter (BEC). Key areas of focus include: carry select adders, binary excess converters, high-speed adders, area optimization, power consumption, and VLSI implementation.- Quote paper
- Prajakta Wasekar (Author), Prof. U.M. Gokhale (Author), 2012, High Performance Carry Select Adder Using Binary Excess Converter, Munich, GRIN Verlag, https://www.grin.com/document/288145
