Adders are one of the widely used digital components in digital integrated circuit design. Addition is the basic operation used in almost all computational systems. Therefore, the efficient implementation and design of arithmetic units requires the binary adder structures to be implemented in an equally efficient manner. A ripple carry adder has smaller area but less speed. A carry look-ahead adder is faster though its area requirements are high. Carry select adders (CSLA) lie in middle. In this work a novel carry select adder using Binary Excess Converter (BEC) is proposed. It provides good compromise between cost and performance thereby establishing a proper trade-off between time and area complexities. In this work Tanner EDA is used for the comparison of all adders – Ripple carry adder, Bitwise carry select adder, Square root carry select adder, proposed carry select adder using BEC.
Table of Contents
I. Introduction
II. Regular Carry Select Adder
III. Binary Excess Convertor (BEC)
IV. Proposed Carry Select Adder
V. Results
VI. Conclusion
VII. References
Objectives and Research Themes
This work aims to design and implement a high-performance, area-efficient, and low-power Carry Select Adder (CSLA) by utilizing a Binary Excess Converter (BEC) to replace traditional Ripple Carry Adder (RCA) structures, thereby optimizing the trade-off between speed, power consumption, and silicon area.
- Optimization of CSLA architecture for VLSI design.
- Reduction of gate-level complexity using Binary Excess Converters.
- Comparative analysis of various adder types including Ripple Carry and Square Root CSLA.
- Performance evaluation based on power dissipation, area (MOSFET count), and propagation delay.
- Application of Tanner EDA and Microwind tools for circuit simulation and layout generation.
Excerpt from the Book
III. Binary Excess Convertor (BEC)
The main idea of this work is to use BEC instead of the RCA with Cin=1 in order to reduce the area and power consumption of the regular CSLA. Fig 2 shows a 4bit BEC logic diagram consisting of XOR, AND gates and an inverter. Fig.3 a) shows the schematic view of 4-bit BEC. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder (FA) structure.
Summary of Chapters
I. Introduction: Outlines the necessity for high-speed arithmetic units in modern VLSI design and identifies the limitations of traditional adders regarding power, area, and speed.
II. Regular Carry Select Adder: Explains the operational principles and challenges of the standard Carry Select Adder, particularly focusing on propagation delay and logic style optimization.
III. Binary Excess Convertor (BEC): Details the proposed gate-level modification replacing standard adders with a BEC structure to improve efficiency.
IV. Proposed Carry Select Adder: Describes the integration of BEC into the CSLA architecture to achieve significant reductions in area and power consumption.
V. Results: Presents simulation data comparing the regular and modified 16-bit CSLA performance using TSMC 50nm technology.
VI. Conclusion: Summarizes the performance gains achieved by the proposed method and suggests directions for future research.
Keywords
Carry Select Adder, Binary Excess Converter, Fast Adder, VLSI Design, Power Consumption, Propagation Delay, Gate-level Modification, MOSFET, Arithmetic Units, Tanner EDA, CMOS, Circuit Optimization, Low-power Design.
Frequently Asked Questions
What is the core focus of this research?
The research focuses on enhancing the performance of Carry Select Adders by reducing their area and power consumption through the implementation of a Binary Excess Converter (BEC).
What are the primary challenges addressed?
The study addresses the critical trade-off between speed, power dissipation, and physical area in digital integrated circuit design for arithmetic units.
What is the main objective of the proposed design?
The primary objective is to develop an efficient, low-power adder architecture that outperforms the regular Square Root Carry Select Adder (SQRT CSLA) in terms of area and power.
Which methodology is employed in this study?
The authors use gate-level architectural modifications, specifically replacing Ripple Carry Adders with BEC structures, and validate the results using Tanner EDA software.
What does the main body cover?
It covers the theoretical background of adders, the specific BEC logic design, the integration of this logic into a 16-bit CSLA, and a comparative analysis of experimental results.
Which terms best characterize this paper?
Key terms include Carry Select Adder, Binary Excess Converter, VLSI Design, Area Efficiency, and Low-power Consumption.
How does the BEC contribute to the adder's performance?
The BEC requires fewer logic gates compared to a standard n-bit Full Adder, which directly contributes to a smaller total area and reduced power demand.
What specific improvements were observed in the 16-bit model?
The proposed 16-bit modified CSLA showed a 15% reduction in area and a 20% reduction in power consumption compared to the regular CSLA design.
- Quote paper
- Prajakta Wasekar (Author), Prof. U.M. Gokhale (Author), 2012, High Performance Carry Select Adder Using Binary Excess Converter, Munich, GRIN Verlag, https://www.grin.com/document/288145
