Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow.
The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes.
The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment.
The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing.
Table of Contents
1. INTRODUCTION
1.1 INTRODUCTION TO TESTING OF VLSI CIRCUITS
1.2 MOTIVATION FOR THE RESEARCH
1.3 OBJECTIVES OF THE RESEARCH
1.4 IMPORTANCE OF TESTING
1.5 TESTING AND VLSI LIFE CYCLE
1.5.1 VLSI Development Process
1.5.1.1 Design verification
1.5.1.2 Yield and reject rate
1.5.2 Electronic System Manufacturing Process
1.5.2.1 System-level operation
1.6 CHALLENGES
1.6.1 Test Generation
1.6.2 Fault Models
1.7 REVIEW OF VLSI TEST TECHNOLOGY
1.7.1 Automatic Test Equipment
1.7.2 Automatic Test Pattern Generation
1.7.3 Fault Simulation
1.7.4 Design For Testability
1.7.4.1 Stand-alone BIST
1.7.4.2 Hybrid BIST
1.8 TEST DATA COMPRESSION
1.8.1 Automatic Test Equipment
1.8.2 Test Stimulus Compression
1.8.2.1 Code-based schemes
1.8.2.2 Dictionary code (fixed-to-fixed)
1.8.2.3 Huffman code (fixed-to-variable)
1.8.2.4 Run length code (variable-to-fixed)
1.8.2.5 Golomb code (variable-to-variable)
1.8.2.6 Linear-decompression-based schemes
1.8.2.7 Sequential linear decompressors.
1.8.2.8 Broadcast-scan-based schemes
1.8.3 Test Response Compaction
1.8.3.1 Space compaction
1.8.3.2 Time compaction
1.8.3.3 Mixed time and space compaction
1.9 ANALYSIS OF ALGORITHMS
2. LITERATURE SURVEY
2.1 INTRODUCTION
2.2 CODE BASED SCHEMES
2.2.1 Block to Block Codes
2.2.2 Block-to-Variable Codes
2.2.3 Variable-to-Block Codes
2.2.4 Variable-to-Variable Codes
2.3 LINEAR-DECOMPRESSOR-BASED SCHEMES
2.3.1 Combinational Linear Decompressors
2.3.2 Sequential Linear Decompressors
2.3.3 Combined Linear and Nonlinear Decompressors
2.4 BROADCAST-SCAN-BASED SCHEMES
2.4.1 Static Reconfiguration
2.4.2 Dynamic Reconfiguration
2.5 COMPRESSION ALGORITHM
2.5.1 The Dictionary Based Compression Techniques
2.5.2 Huffman Coding Based Compression Techniques
2.5.3 Run Length Based Compression Techniques
3. A MIXED SELECTED SELECTIVE HUFFMAN AND RUN LENGTH CODING ALGORITHM
3.1 INTRODUCTION
3.2 HUFFMAN CODING
3.2.1 Huffman Code Properties
3.2.2 Prefix Property
3.3 RUN LENGTH CODING
3.4 A MIXED SELECTED SELECTIVE HUFFMAN AND RUN LENGTH CODING ALGORITHM
3.4.1 Compression Algorithm
3.4.2 Decompression Algorithm
3.5 IMPLEMENTATION RESULTS AND DISCUSSION
3.6 SUMMARY
4. COMBINED COMPATIBLE BLOCK AND RUN LENGTH CODING ALGORITHM
4.1 INTRODUCTION
4.2 BLOCK CODING TECHNIQUE
4.3 TEST DATA COMPRESSION USING COMPATIBLE BLOCK CODE AND RUN LENGTH CODES
4.3.1 Compatible Block Coding
4.3.2 Run Length Coding
4.3.3 CCBRLC Compression Algorithm
4.3.4 CCBRLC Decompression Algorithm
4.4 IMPLEMENTATION RESULTS AND DISCUSSION
4.5 SUMMARY
5. A MODIFIED RUN LENGTH CODING TECHNIQUE BASED ON MULTI-LEVEL SELECTIVE HUFFMAN CODING ALGORITHM
5.1 INTRODUCTION
5.2 MODIFIED RUN LENGTH CODE BASED MULTILEVEL SELECTIVE HUFFMAN CODING ALGORITHM
5.2.1 Modified Run Length Coding
5.2.2 Multilevel Selective Huffman Coding Algorithm
5.3 COMPRESSION ALGORITHM
5.4 DECOMPRESSION ALGORITHM
5.4.1 Decoder architecture
5.5 IMPLEMENTATION RESULTS AND DISCUSSION
5.5.1 Compression Algorithms
5.5.2 Decompression Logic
5.5.2.1 FPGA design simulation
5.5.2.2 FPGA design synthesize
5.5.2.3 ASIC design using cadence
5.6 SUMMARY
6. A HYBRID OF BITMASK DICTIONARY AND 2n PATTERN RUNLENGTH CODING ALGORITHM
6.1 INTRODUCTION
6.2 BITMASK BASED DICTIONARY COMPRESSION
6.3 2n PATTERN RUN LENGTH CODING
6.4 A HYBRID OF BITMASK DICTIONARY AND 2n PATTERN RUNLENGTH CODING ALGORITHM
6.4.1 BDPRLC Compression Algorithm
6.4.2 BDPRLC Decompression Algorithm
6.5 IMPLEMENTATION RESULTS AND DISCUSSION
6.5.1 BDPRLC Compression algorithm
6.5.2 BDPRLC Decompression Logic
6.5.2.1 FPGA design simulation
6.5.2.2 FPGA design synthesize
6.5.2.3 ASIC design using cadence
6.6 SUMMARY
7. CONCLUSION AND FUTURE WORKS
7.1 INTRODUCTION
7.2 FUTURE WORKS
Objectives & Research Themes
The primary research objective is to develop novel test data compression algorithms for VLSI circuits to reduce data volume, memory requirements, and test application time. The research focuses on hybridizing established code-based schemes, such as Huffman coding, Run Length Coding, Compatible Block Coding, and Bitmask-Dictionary methods, to improve compression ratios during scan-based testing.
- Reduction of test data volume in VLSI circuits.
- Minimization of tester memory requirements and test time.
- Hybridization of entropy coding techniques (Huffman, RLC).
- Integration of bitmask-dictionary and block coding strategies.
- Hardware-level validation of decompression logic via FPGA and ASIC synthesis.
Book Excerpt
1.1 INTRODUCTION TO TESTING OF VLSI CIRCUITS
The role of testing is to detect the problems in a circuit and the role of diagnosis is to determine where the problem has occurred. Correctness and effectiveness of testing are the most important characteristics of quality products. According to Moore’s law, the number of transistors integrated per square inch on a die has been doubled every 18 months since the invention of integrated circuit. The growing size and complexity of the transistors pose many new challenges that make the testing of Very-Large-Scale-Integrated (VLSI) circuits, relevant. As these trends continue with the development of semiconductor manufacturing technology, the requirements of digital VLSI circuits have also brought in many challenges during the manufacturing test. This is due to the large and complex chips that require enormous amount of test data and dissipate a significant amount of power during the test thus resulting in considerable increase in test cost. This chapter introduces certain important concepts in testing of digital VLSI circuits and highlights the significance of minimizing test data volume during the test.
Summary of Chapters
1. INTRODUCTION: Introduces the necessity of testing VLSI circuits and defines the primary research objectives regarding test data compression.
2. LITERATURE SURVEY: Reviews existing techniques for test data compression, including code-based and linear-decompression schemes.
3. A MIXED SELECTED SELECTIVE HUFFMAN AND RUN LENGTH CODING ALGORITHM: Proposes a hybrid encoding scheme combining Selective Huffman and Run Length Coding to improve compression ratios.
4. COMBINED COMPATIBLE BLOCK AND RUN LENGTH CODING ALGORITHM: Introduces a compression algorithm that merges compatible blocks and applies RLC to reduce test data volume.
5. A MODIFIED RUN LENGTH CODING TECHNIQUE BASED ON MULTI-LEVEL SELECTIVE HUFFMAN CODING ALGORITHM: Details a multi-level approach to compression, including FPGA-based decoder architecture and simulation results.
6. A HYBRID OF BITMASK DICTIONARY AND 2n PATTERN RUNLENGTH CODING ALGORITHM: Presents an advanced compression method using bitmask-dictionary techniques combined with pattern run-length coding, achieving high compression efficiency.
7. CONCLUSION AND FUTURE WORKS: Summarizes the research outcomes and discusses potential future research directions in test data compression.
Keywords
VLSI, Test Data Compression, Scan Testing, Huffman Coding, Run Length Coding, Compatible Block Coding, Bitmask-Dictionary, BIST, Decompression, ISCAS Benchmark Circuits, FPGA, Synthesis, Fault Coverage, Test Application Time, Memory Requirements.
Frequently Asked Questions
What is the core focus of this research?
The research focuses on addressing the challenges of increasing test data volumes in modern VLSI systems by developing efficient, lossless test data compression and decompression techniques.
What are the primary themes addressed in this book?
The primary themes include test data volume reduction, memory optimization, scan-based test architecture, and the design of effective on-chip decompression logic.
What is the main objective of the proposed algorithms?
The main objective is to improve the compression ratio to decrease the amount of test data stored on the tester, thereby reducing test time and testing costs without degrading fault coverage.
Which scientific methods are primarily utilized in this work?
The author uses a variety of coding techniques including Selective Huffman Coding, Run Length Coding (RLC), Compatible Block Coding, and Bitmask-Dictionary methods, validated through MATLAB simulations and HDL-based hardware synthesis.
What is explored in the main body of the text?
The main body systematically explores four distinct hybrid compression algorithms (SSHRLC, CCBRLC, MRLMHC, BDPRLC), comparing them against existing methods using standard ISCAS benchmark circuits.
Which keywords characterize this research?
Key terms include VLSI, Test Data Compression, BIST, Huffman Coding, and Bitmask-Dictionary, which reflect the hardware-oriented approach to data compression.
How is the efficiency of the proposed algorithms validated?
Efficiency is validated by measuring the compression ratios achieved across multiple ISCAS benchmark circuits and comparing these results against standard existing methods.
What is the specific contribution regarding the decompression architecture?
The author demonstrates that the decompression logic for the proposed algorithms can be implemented in hardware (FPGA/ASIC) with optimized area and power, making them suitable for real-world Built-In Self-Test (BIST) environments.
- Arbeit zitieren
- Dr. Kalamani Chinnappa Gounder (Autor:in), 2018, Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits, München, GRIN Verlag, https://www.grin.com/document/430834
