Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow.
The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes.
The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment.
The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing.
Inhaltsverzeichnis (Table of Contents)
- ABSTRACT
- INTRODUCTION
- TEST DATA COMPRESSION
- Test Data Compression Techniques
- Advantages of Test Data Compression
- Code Based Test Data Compression
- PROPOSED ALGORITHMS
- Mixed Selected Selective Huffman and Run Length Coding Techniques Algorithm(SSHRLC)
- Combined Compatible Block and Run Length Coding Algorithm(CCBRLC)
- A Modified Run Length Coding Technique Based On Multi-Level Selective Huffman Coding Algorithm(MRLMHC)
- A Hybrid of Bitmask Dictionary and 2" Pattern Run Length Coding Algorithm(BDPRLC)
- SIMULATION RESULTS
- CONCLUSION
- REFERENCES
Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)
The main objective of this work is to develop efficient test data compression techniques for reducing the memory requirements and test time for testing VLSI circuits. These techniques aim to improve the compression ratio by combining different code-based schemes.
- Test data compression techniques for VLSI circuits
- Code-based compression schemes for test data reduction
- Implementation and evaluation of various compression algorithms
- Analysis of compression ratio and performance metrics
- Exploration of VLSI design parameters for implementation in BIST environments
Zusammenfassung der Kapitel (Chapter Summaries)
- ABSTRACT: This chapter provides a brief overview of the research, highlighting the problem of increasing test data volume in VLSI circuits and introducing the proposed solution of hybrid code-based compression techniques.
- INTRODUCTION: This chapter further elaborates on the challenges associated with test data volume in VLSI circuits, emphasizing the need for efficient test data compression methods. The chapter also presents a background on test data compression techniques and their advantages.
- TEST DATA COMPRESSION: This chapter delves into the fundamental concepts of test data compression, exploring various techniques, including code-based methods. It highlights the benefits of test data compression and its role in enhancing testability of VLSI circuits.
- PROPOSED ALGORITHMS: This chapter presents four different proposed compression algorithms: SSHRLC, CCBRLC, MRLMHC, and BDPRLC. It outlines the principles and implementations of each algorithm, highlighting their unique features and potential for improving compression ratio.
- SIMULATION RESULTS: This chapter presents the simulation results obtained from applying the proposed algorithms to benchmark circuits. It analyzes the compression ratio achieved by each algorithm and compares them with existing methods. The chapter also discusses the implementation and validation of decompression logic for the proposed algorithms.
Schlüsselwörter (Keywords)
This research focuses on test data compression techniques for VLSI circuits, specifically exploring code-based schemes for encoding and decoding test data. Key themes include: test data compression, code-based compression, Huffman coding, Run Length Coding, VLSI testing, BIST, compression ratio, decompression logic, benchmark circuits, and VLSI design parameters.
- Quote paper
- Dr. Kalamani Chinnappa Gounder (Author), 2018, Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits, Munich, GRIN Verlag, https://www.grin.com/document/430834
