Applications of Artificial Intelligence in Physical Design and Testing of Very Large Scale Integration

Academic Paper , 2024 , 42 Pages

Computer Sciences - Artificial Intelligence

Our book provides a succinct summary of Artificial Intelligence applications across multiple Very-Large-Scale Integration (VLSI) design flow and testing domains. One technique of fabrication, CMOS technology, is where the evolution of VLSI begins. Complementary Metal Oxide Semiconductor (CMOS) offers numerous advantages but to pack high number of Integrated Circuits (ICs) in compact geometries, VLSI enters into picture. We can design VLSI using Computer Aided Tools like Electronic Design Automation (EDA). VLSI design consists of two primary parts: the front end and the back end. Fabrication procedures such as Architectural Design, Gate Level Design, Simulation, Hardware Descriptive Language (HDL), Circuit Level Design, Verification, and Fabrication are included at the back end. Descriptive languages for hardware are the main emphasis of front end. HDL is essential to system design use because it enables the behavior of the core system to be verified and modelled prior to the design being converted by synthesis tools into physical hardware, such as gates and wires. Different chemical and physical processes are needed for the backend operations. It is possible to create Artificial Intelligence algorithms that aid in raising the yield of physical processes. Artificial Intelligence and Machine Learning (AI-ML) algorithms assist in predicting parametric yield at the device level. Furthermore AI-ML algorithms are implemented at the gate level to analyse the total latency of the gate connection. Also, AI-ML algorithms can be used at the circuit level to maximize the performance of circuits. A combination of AI-ML algorithms in EDA tools allows for the examination of propagation delay, power leakage, etc. During lithography, transfer learning can be used to produce data. Effective testing becomes a crucial task as electronic systems and components becoming more complex, striking a balance between the need for high quality and cost effectiveness. In spite of its labour-intensive nature, testing has become a critical technique for cutting total costs in the production of electronic systems, boards, and VLSI chips. It plays a critical role in ensuring that VLSI design satisfy quality requirement by identifying circuit faults. In order to handle the complexity of contemporary systems, recent developments have incorporated machine learning (ML) and artificial intelligence (AI) into established VLSI testing techniques.

Inhaltsverzeichnis (Table of Contents)

• 1 Evolution of Very-Large-Scale Integration (VLSI)
• 1.1 Introduction
• 1.2 Complementary Metal Oxide Semiconductor (CMOS)
• 1.2.1 CMOS Technology
• 1.2.2 Advantages of CMOS Technology
• 1.3 Why Very-Large-Scale Integration (VLSI)?
• 1.4 Electronic Design Automation (EDA)
• 1.5 Conclusion
• 2 VLSI Design Flow
• 2.1 Introduction
• 2.2 Design Specification
• 2.3 Architecture Design Level
• 2.4 Gate Level Design
• 2.5 Circuit Level Design
• 2.6 Hardware Descriptive Language (HDL) Coding
• 2.7 Circuit Simulation and Analysis
• 2.8 Fabrication
• 2.9 Conclusion
• 3 Use of AI in VLSI Design Flow
• 3.1 Introduction
• 3.2 Artificial Intelligence at Design Level
• 3.3 Artificial Intelligence at Gate Level
• 3.4 Artificial Intelligence at Circuit Level
• 3.5 Artificial Intelligence at Resistor Transistor Logic (RTL) Level
• 3.6 Artificial Intelligence at Post Layout Simulation
• 3.7 Artificial Intelligence in Manufacturing
• 3.7.1 Artificial Intelligence for Lithography
• 3.8 Conclusion
• 4 VLSI Testing
• 4.1 Introduction
• 4.2 Testing Techniques
• 4.2.1 Design for Testability (DFT)
• 4.2.2 Automatic Test Pattern Generation (ATPG)
• 4.2.3 Built-in-Self-Test (BIST)
• 4.3 Very-Large-Scale Integration (VLSI) Testing Challenges
• 4.4 Enhancing Fault Detection with Machine Learning
• 4.5 Upcoming Prospect of Machine Learning in Very-Large-Scale Integration (VLSI)
• 4.6 Conclusion
• 5 Role of AI in SoC Design
• 5.1 Introduction
• 5.2 Design Elements of SoC
• 5.3 Combination of AI and SoC
• 5.3.1 Custom Hardware Acceleration
• 5.3.2 Optimizing Memory
• 5.3.3 Optimizing Power
• 5.3.4 Security
• 5.3.5 Connection of Data in Real Time
• 5.4 High Level Architecture of an System on Chip (SoC) Design
• 5.5 Conclusion
• 6 Summary

Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)

This book aims to provide a concise overview of Artificial Intelligence applications within the Very-Large-Scale Integration (VLSI) design flow and testing processes. It explores how AI and Machine Learning enhance various stages, from design to manufacturing and testing.

• Evolution and advantages of CMOS technology in VLSI.
• The VLSI design flow and the integration of AI at different levels.
• AI-enhanced VLSI testing methodologies (DFT, ATPG, BIST).
• The role of AI in optimizing System-on-Chip (SoC) design.
• The use of AI to improve the yield and efficiency of VLSI manufacturing processes.

Zusammenfassung der Kapitel (Chapter Summaries)

Chapter 1 introduces the evolution of VLSI, focusing on CMOS technology and its advantages. Chapter 2 details the VLSI design flow, outlining each stage from design specification to fabrication. Chapter 3 explores the various applications of AI throughout the VLSI design flow, highlighting its impact on design, gate, circuit, and RTL levels, as well as manufacturing processes like lithography. Chapter 4 examines VLSI testing techniques and how AI and machine learning enhance fault detection and improve overall testing methodologies like DFT, ATPG, and BIST. Chapter 5 discusses the transformative role of AI in SoC design, emphasizing efficiency improvements and the creation of more robust systems.

Schlüsselwörter (Keywords)

Complementary Metal Oxide Semiconductor (CMOS), Electronic Design Automation (EDA), Artificial Intelligence (AI), Machine Learning (ML), Very-Large-Scale Integration (VLSI), Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), Built-in-Self-Test (BIST), System-on-Chip (SoC).

• Authors: Hardik Modi (Author), Vanshika Jain (Author), Diya Gangurde (Author), Dharmendra Chauhan (Author), Sagarkumar Patel (Author)
• Publication Year: 2024
• Pages: 42
• Catalog Number: V1509759
• ISBN (PDF): 9783389077528
• ISBN (Book): 9783389077535
• Language: English
• Tags: CMOS,, EDA, ATPG, DFT, BIST, SoC