This laboratory results shows the Verilog hardware design language (HDL) and Finite State Machine to control a pedestrian crossing controller and its modification. In session-1, simple Verilog program is simulated and then tested on Coolrunner-II board. In this session the controller three outside world input which are Clock (CLK), Reset (RESET), Pedestrian (PED) and three output which are Red light (RED), Amber light (AMBER), Green light (GREEN).
In session-2, some modifications are done on Verilog program used in session-1 and then again simulated and tested on Coolrunner-II board. In this session the controller 7 segment displays is used to see changes in pelstate, while running modified Verilog program on Coolrunner-II board and Carsensor outside world input has been introduced in modified Verilog program. In this modified Verilog program, number of pelstate has been increased.
This laboratory session provides a good opportunity to learn Xilinx ISE Design Suit software and introduce to Coolrunner-II board.
Table of Contents
Introduction
Session – I
Verilog modules and ‘ucf’ file for session – I
State Diagram of Session – I
Simulation for Session – I
CPLD Fitting Report for Session – I
Working of Program on Coolrunner – II
Session – II
State Diagram for Session – II
Verilog modules and ‘ucf’ file for session – II
Simulation for Session – II
CPLD Fitting Report for Session – II
Working of Program on Coolrunner – II
Research Objectives and Themes
This report documents the design, simulation, and implementation of a pedestrian crossing controller using Verilog Hardware Description Language (HDL) on a Coolrunner-II CPLD board. The primary objective is to develop a robust Finite State Machine (FSM) that manages traffic light sequences based on external inputs, with a focus on both initial controller design and subsequent functional modifications.
- Design and simulation of a basic Finite State Machine for traffic light control.
- Implementation of hardware constraints and CPLD fitting for digital systems.
- Modification of existing FSM logic to incorporate advanced sensor inputs.
- Integration of seven-segment displays for monitoring system states.
Excerpt from the Book
Introduction
This laboratory results shows the Verilog hardware design language (HDL) and Finite State Machine to control a pedestrian crossing controller and its modification. In session – 1, simple Verilog program is simulated and then tested on Coolrunner – II board. In this session the controller three outside world input which are Clock (CLK), Reset (RESET), Pedestrian (PED) and three output which are Red light (RED), Amber light (AMBER), Green light (GREEN).
In session – 2, some modifications are done on Verilog program used in session – 1 and then again simulated and tested on Coolrunner – II board. In this session the controller 7 segment displays is used to see changes in pelstate, while running modified Verilog program on Coolrunner – II board and Carsensor outside world input has been introduced in modified Verilog program. In this modified Verilog program, number of pelstate has been increased.
This laboratory session provides a good opportunity to learn Xilinx ISE Design Suit software and introduce to Coolrunner – II board.
Summary of Chapters
Introduction: Provides an overview of the laboratory work focusing on developing and modifying a Verilog-based pedestrian crossing controller.
Session – I: Details the design of the initial FSM, including Verilog code, state diagrams, simulation results, and CPLD board implementation.
Session – II: Describes the refined controller design featuring increased state complexity, additional car sensor inputs, and integration with seven-segment displays.
Keywords
Verilog, HDL, Finite State Machine, FSM, Pedestrian Crossing Controller, Coolrunner-II, CPLD, Xilinx ISE, Digital System Design, Hardware Simulation, Traffic Light Control, Hardware Constraints, Logic Synthesis.
Frequently Asked Questions
What is the core focus of this technical report?
The report focuses on the design, simulation, and hardware implementation of a digital pedestrian crossing controller using Verilog HDL and CPLD technology.
Which key components are involved in the controller design?
The design utilizes Finite State Machines, external inputs like Clock, Reset, Pedestrian button, and Car sensors, as well as outputs like traffic lights and seven-segment displays.
What is the primary goal of the two sessions described?
The goal is to develop an initial working controller in the first session and then modify the Verilog code to handle more complex scenarios in the second session.
Which software and hardware tools were utilized for this project?
The project used Xilinx ISE Design Suite software and the Coolrunner-II CPLD development board.
How is the FSM logic verified?
The logic is verified through digital simulations that monitor state transitions and signal timing, followed by physical testing on the CPLD board.
Which specific methodology is applied for the system design?
The system is designed using the Moore machine model for state logic and Verilog hardware description for module synthesis.
What is the purpose of the 'Carsensor' introduced in the second session?
The car sensor input modifies the FSM flow, allowing the controller to dynamically adjust traffic light states based on detected vehicular traffic.
How do the 'pelstate' registers change between sessions?
The state complexity increases from the first to the second session, requiring an expansion in the bit-width of the state register to accommodate additional operational states.
- Citation du texte
- Ninad Gondhalekar (Auteur), 2013, Verilog Design of a Pedestrian Crossing, Munich, GRIN Verlag, https://www.grin.com/document/284210
